1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC), and more particularly to a method of simulating an intellectual property (IP) core included in the semiconductor IC at a system-on-chip (SoC) level.
2. Description of the Related Art
A SoC and/or an application specified integrated circuit (ASIC) design may have problems of integration errors when IP cores are integrated into the SoC/ASIC chip. Thus, expense and time for testing the SOC/ASIC design is increased. Additionally, test guides distributed to the customers with the IP cores are difficult for the customers to understand. Real net lists of the IP cores are required for testing the IP cores of the SoC/ASIC chip.
Customers may omit the test of the SoC/ASIC design because time-to-market is critical. Probability of the problems due to integration errors of the IP cores is high because the test is not performed when the customers cannot be provided with the net lists, for example, when the customers use the IP cores abroad.
Accordingly, an IP core model substituting the real IP core is required for testing the real IP core.